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100mhz bus frequency Chipsets features
comparison
Last update July 2, 1998
Intel 440BX AGP Chipset
The
Intel ® 440BX AGPset includes the 82443BX Host
Bridge and the 82371EB PIIX4E for the I/O subsystem. The
82443BX features include:
• Support dual Pentium
II processor configurations • Support full symmetric
Multi-processor (SMP) • 64-bit GTL+ based Host Bus
Interface • 32-bit Host address Support • 64-bit
Memory Interface optimized for PC100 SDRAM • 32-bit
Primary PCI Bus Interface (PCI) with integrated PCI
arbiter • AGP Interface (AGP) with 133 MHz (X2) data
transfer capability • Mobile and "Deep Green" Desktop
power management support
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The following block diagram shows a typical platform
based on the Intel ® 440BX AGPset. The 82443BX host bus
interface supports up to two Pentium II processors at the
maximum bus frequency of 100 MHz. The 82443BX provides an
optimized 64-bit DRAM interface. This interface is implemented
as a 3.3V-only interface that supports only 3V DRAM
technology. Two copies of the MA, and CS# signals drive a
maximum of two DIMMs each; providing unbuffered high
performance at 100 MHz. The 2443BX provides interface to PCI
operating at 33 MHz. This interface implementation is
compliant with PCI Rev 2.1 Specification. The 82443BX AGP
interface implementation is based on Rev 1.0 of the AGP
Specification. The AGP nterface supports 133 MHz (AGP 2X) data
transfer rates and can be used as a Secondary PCI interface
operating at 66 MHz/3.3V supporting only a single PCI
agent.
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Intel 440BX AGP Chipset Block Diagram

As you can see the BX Chipset is not very different
of a LX Chipset. The main difference between the LX and BX
Chipsets is that the later support a bus frequency of 100mhz,
Does this make a great performance improvment? Not realy,
because the L2 cache is installed on the CPU cartridge on the
slot 1 Pentium II architecture it is clocked and half the CPU
frequency so cloking the CPU to 4.5 times 66mhz or 3 times
100mhz for a PII 300mhz will give the same final results with
a L2 cache frequency of 150mhz, so, there are no real
performance gain here ! However, if used on Socket 7, this
chipset would give a real boost to the L2 cache memory because
on these motherboards the memory is clocked at 66mhz,
therefore, 100mhz bus speed representing a 50% incrrease in
speed over the standard 66mhz bus architecture this should
give a real good push to the L2 cache memory especially when
used with PC100 SDram memory.
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Aladdin Pro II / M1621/ M15X3
The Aladdin
Pro II is a new generation Pentium II class system
Chipset. It consists of two BGA packed chips, the M1621 and
M1533 or M1543. The M1621 is an AGP, memory and I/O controller
and a data path with multi-port buffers for data acceleration.
With an external I/O APIC controller, it can support multiple
Pentium II processors.
The M1533 provides a bridge between the PCI bus and
ISA bus. It includes power management unit, ACPI, deep green
function, 2-channel dedicated Ultra-33 IDE master controller,
2-port USB controller, SMBus controller, and PS2
Keyboard/Mouse controller. The M1543 integrates ACPI, green
function, 2-channel dedicated Ultra-33 IDE Master controller,
2-port USB controller, SMBus controller, PS/2 keyboard/mouse
controller and Super I/O (Floppy Disk Controller, 2 serial
port/1 parallel port) support.
Aladdin Pro employs various techniques to improve
the memory and I/O throughput to match up with the advanced
super-scalar, super-pipelined Pentium II class processors. On
the memory subsystem side, the Pentium II data bus utilization
is minimized. The pipelined memory cycle design helps hidden
precharge latency and refresh cycles. Different ways of
configurations optimize the performance for a wide range of
memory size. On the I/O subsystem side, deep buffers shadow
the latency for both PCI devices initiated master read and
write. To support the 3D graphics function, M1621 supports a
66 Mhz graphics PCI bus, and 1x/2x AGP mode.
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VIA Apollo Pro
VIA Apollo
Pro supercedes VIA's Apollo P6 (introduced in 1996) and is
the industry's first available alternative Slot-1 core logic
chipset. The north bridge chip of the new chipset is called
the VT82C691. Complimenting VIA's new Apollo Pro north bridge
core logic chip is a new south bridge, the VT82C596, which
also upgrades the Apollo MVP3 Socket-7 chipset (VT82C598MVP),
introduced Jan 14, 1998.
The Apollo Pro is a two-chip set supporting both
desktop and mobile designs. It consists of the (VT82C691)
north bridge controller and the also new (VT82C596) south
bridge. The north bridge features 100MHz support for Slot-1
processors. It also provides synchronous and
pseudo-synchronous CPU/AGP/PCI operation and support for the
full range of currently available DRAMs including PC100
SDRAM.
The new VT82C596 south bridge supports both Socket-7
and Slot-1 PC system designs and is the first device offering
support for the emerging ATA-66 disk drive interface standard.
ATA-66, also known as ULTRA DMA 66, effectively doubles drive
data transfer rates. The new south bridge also provides PC98
ACPI, UDMA and USB support. It works with the advanced power
management features of VIA's currently available north bridge
chips including suspend-to-DRAM and independent clock controls
for system buses.
By reading the informations and comparing the
features of this Chipset we can easily see that this Chipset
is the most advanced and the most feature packed of all
available Pentium II slot-1 logic cores !
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The following table
summarize all the features of the 440BX Chipset and compares
it to the VIA Apollo Pro and Ali Aladdin Pro II Chipsets
which are both 100mhz Chipsets.
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100mhz Chipsets Features
comparison |
| FEATURE |
VIA Apollo
Pro |
440BX |
Ali Pro
II |
|
Processor
Support |
| Chipset no: |
VIA Apollo Pro |
440BX |
Ali Pro II |
| Pentium II
® |
Y |
Y |
Y |
|
Bus Features
Support |
| Chipset no: |
VIA Apollo Pro |
440BX |
Ali Pro II |
| PCI 2.1
|
Y |
Y |
Y |
| AGP
Support |
Y 1X/2X |
Y 1X/2X |
Y 1X/2X |
| Bus speed
Mhz |
66/100 |
66/100 |
60/66/100 |
| Async. PCI Bus
speed |
Y |
N |
N |
|
L2
Cache |
| Chipset no: |
VIA Apollo Pro |
440BX |
Ali Pro II |
| Max. Cache
size |
Built in CPU
Cartridge |
Built in CPU
Cartridge |
Built in CPU
Cartridge |
| Cache
type |
Built in CPU
Cartridge |
Built in CPU
Cartridge |
Built in CPU
Cartridge |
| Cachable
area |
Built in CPU
Cartridge |
Built in CPU
Cartridge |
Built in CPU
Cartridge |
| Cache
Timing |
Built in CPU
Cartridge |
Built in CPU
Cartridge |
Built in CPU
Cartridge |
|
DRAM
Interface |
| Chipset no: |
VIA Apollo Pro |
440BX |
Ali Pro II |
| Max.
DRAM |
1GB EDO/SDRAM |
512MB SDram 1G EDO |
1G SDram 2G
EDO/FPM |
|
EDO Timing |
5-2-2-2-2-2-2-2 |
x-2-2-2-2-2-2-2 |
x-2-2-2-2-2-2-2 |
|
SDRAM page
hit |
6-1-1-1-2-1-1-1 |
x-1-1-1-1-1-1-1 |
x-1-1-1-1-1-1-1 |
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Supported Memory
Types |
| Chipset no: |
VIA Apollo Pro |
440BX |
Ali Pro II |
| FPM |
Y |
N |
Y |
| ECC |
Y |
Y |
Y |
| EDO |
Y |
Y |
Y |
| BEDO |
N |
N |
N |
| SDRAM |
Y |
Y |
Y |
| DDR
SDRAM |
Y |
N |
N |
| BDDR
SDRAM |
Y |
N |
N |
| ESDRAM |
Y |
N |
N |
|
Integrated
Feautres |
| Chipset no: |
VIA Apollo Pro |
440BX |
Ali Pro II |
| Ultra
DMA-33 |
Y |
Y |
Y |
| Ultra
DMA-66 |
Y |
N |
N |
| Highest Transfer
rate |
PIO-6 DMA-4 |
PIO-5, DMA-3 |
PIO-4, DMA-2 |
| EIDE
Interface |
Y |
Y |
Y |
| USB |
Y |
Y |
Y |
| Integrated
KBC |
Y |
Y |
Y |
| Integrated
RTC |
Y |
Y |
Y |
| Number of
chip |
2 (VT82C691/VT82C596) |
2 (82443BX/82371EB) |
2 (M1621/M15X3) |
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Miscellaneous |
| Chipset no: |
VIA Apollo Pro |
440BX |
Ali Pro II |
| ACPI
Unit |
Y |
Y |
Y |
| PC97
Compliance |
Y (PC97/PC98} |
Y |
Y |
*Intel doesn't officially support non-Intel
processors. | | | |
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